"Optimising Transformations for Hardware Compilation", to appear in proceedings of
ACACES 2005, the First International Summer School on
Advanced Computer Architecture and Compilation for Embedded Systems.
Ray C.C. Cheung,
and and P.Y.K. Cheung,
"A Scalable Hardware Architecture for Prime Number Validation", proceedings of the IEEE International Conference on Field Programmable Technology (FPT), Brisbane, Australia, 2004.
A. Brown, "Optimising Transformations for Hardware Compilation", Master's Thesis,
Department of Computing, Imperial College London, 2005.
Ray C.C. Cheung and A. Brown, "A Scalable System-on-a-chip Architecture for Prime Number Validation", proceedings of IEE SoC Design, Test and Technology Postgraduate Seminar, Loughborough, United Kingdom, 2004.
- General Interest